The ATPG tool may generate vectors that exercise logic in a manner that does not occur in functional mode. During capture, one or more clocks might be pulsed at the same time.This means that if multiple clocks are used within the same scan chain, there is a danger of clock skew between the clock domains during shift. When data is shifted through the scan chains, all clocks are pulsed at the same frequency and at the same time.During a scan-based manufacturing test, however, the clocks might be operated in a different way, since in test mode the clocks are delivered by the automatic test equipment (ATE) and internal clock generators and controls are bypassed. Alternatively, resynchronization logic may be used to control data transfer between clock domains that operate truly asynchronously. During functional operation, internal clock generators may also manage internal clock skew in order to ensure proper functional operation. Clock control logic may be designed to pulse various clocks in a specific sequence or to ensure that certain clocks are not pulsed at the same time.
#Multiclock time how to#
This article discusses the trade-offs among various clock test methodology scenarios and offers food for thought on how to proceed in each scenario.įirst and foremost, clock trees are designed with functional operation in mind. These issues need to be taken into consideration during the design stage, since, ultimately, the decisions on how test clocks are designed can have a significant impact on automatic test pattern generation (ATPG). Clock skew can cause difficulties shifting data through the scan chains and can lead to unreliable test patterns. One of the biggest test problems multiple clocks pose when implementing design-for-test (DFT) and generating test patterns is unpredictable clock skew, which can cause test problems in manufacturing.
In test mode, those clocks may be combined into one, or they may all be brought out to separate primary input pins for test. Today's leading-edge system-on-chip (SoC) designs typically have multiple clock domains and, in many cases, multiple internally generated clocks.
0 kommentar(er)
